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RT9610C ? ds9610c-01 april 2016 www.richtek.com 1 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. features ? ? ? ? ? drives two n-mosfets ? ? ? ? ? adaptive shoot-through protection ? ? ? ? ? 0.5 on-resistance, 4a sink current capability ? ? ? ? ? supports high switching frequency ? ? ? ? ? tri-state pwm input for power stage shutdown ? ? ? ? ? output disable function ? ? ? ? ? integrated boost switch ? ? ? ? ? low bias supply current ? ? ? ? ? vcc por feature integrated applications ? core voltage supplies for intel ? / amd ? mobile microprocessors ? high frequency low profile dc/dc converters ? high current low output voltage dc/dc converters ? high input voltage dc/dc converters high voltage synchronous rectified buck mosfet driver for notebook computer general description the RT9610C is a high frequency, dual mosfet driver specifically designed to drive two power n-mosfets in a synchronous-rectified buck converter topology. it is especially suited for mobile computing applications that require high efficiency and excellent thermal performance. this driver, combined with richtek's series of multi-phase buck pwm controllers, provides a complete core voltage regulator solution for advanced microprocessors. the drivers are capable of driving a 3nf load with fast rising/falling time and fast propagation delay. this device implements bootstrapping on the upper gates with only a single external capacitor. this reduces implementation complexity and allows the use of higher performance, cost effective, n-mosfets. adaptive shoot through protection is integrated to prevent both mosfets from conducting simultaneously. the RT9610C is available in wdfn-8l 2x2 package. simplified application circuit ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. RT9610C package type qw : wdfn-8l 2x2 (w-type) lead plating system g : green (halogen free and pb free) marking information 2q : product code w : date code 2qw vcc pwm gnd boot ugate phase lgate RT9610C v cc pwm v core en v in enable
RT9610C 2 ds9610c-01 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 en enable pin. when low, both ugate and lgate are driven low and the normal operation is disabled. 2 phase switch node. connect this pin to the source of the upper mosfet and the drain of the lower mosfet. this pin provides a return path for the upper gate driver. 3 ugate upper gate drive output. connect to the gate of high side power n-mosfet. 4 boot floating bootstrap supply pin for upper gate drive. connect the bootstrap capacitor between this pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. 5 pwm control input for driver. the pwm signal can enter three distinct states during operation. connect this pin to the pwm output of the controller. 6, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 7 lgate lower gate drive output. connect to the gate of the low side power n-mosfet. 8 vcc input supply pin. connect this pin to a 5v bias supply. place a high quality bypass capacitor from this pin to gnd. pin configurations (top view) wdfn-8l 2x2 en boot phase vcc lgate gnd pwm ugate 7 6 5 1 2 3 4 8 gnd 9
RT9610C 3 ds9610c-01 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional block diagram shoot-through protection boot ugate phase por vcc r r tri-state detect pwm en control logic lgate gnd vcc vcc operation por (power on reset) por block detects the voltage at the vcc pin. when the vcc pin voltage is higher than por rising threshold, the por pin output voltage (por output) is high. por output is low when vcc is not higher than por rising threshold. when the por pin voltage is high, ugate and lgate can be controlled by pwm input voltage. if the por pin voltage is low, both ugate and lgate will be pulled to low. tri-state detect when both por output and en pin voltages are high, ugate and lgate can be controlled by pwm input. there are three pwm input modes which are high, low, and shutdown state. if pwm input is within the shutdown window, both ugate and lgate outputs are low. when pwm input is higher than its rising threshold, ugate is high and lgate is low. when pwm input is lower than its falling threshold, ugate is low and lgate is high. control logic control logic block detects whether high side mosfet is turned off by monitoring (ugate - phase) voltages below 1.1v or phase voltage below 2v. to prevent the overlap of the gate drives during the ugate pulls low and the lgate pulls high, low side mosfet can be turned on only after high side mosfet is effectively turned off. shoot-through protection shoot-through protection block implements the dead-time when both high side and low side mosfets are turned off. with shoot-through protection block, high side and low side mosfets are never turned on simultaneously. thus, shoot-through between high side and low side mosfets is prevented.
RT9610C 4 ds9610c-01 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics recommended operating conditions (note 4) ? input voltage, vin ----------------------------------------------------------------------------------------------------------- 4. 5v to 26v ? control voltage, vcc ------------------------------------------------------------------------------------------------------- 4.5v to 5.5v ? ambient temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 85 c ? junction temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 125 c (v cc = 5v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit vcc supply current quiescent current i q pwm pin floating, v en = 3.3v -- 80 -- ? a shutdown current i shdn v en = 0v, pw m = 0v, v cc = 5v -- 0 5 ? a vcc power on reset (por) v porh vcc por rising -- 4.2 4.5 v v porl vcc por falling 3.5 3.84 -- v v porhys hysteresis -- 360 -- mv internal boot switch internal boost switch on resistance r boot vcc to boot, 10ma -- -- 80 ??? absolute maximum ratings (note 1) ? supply voltage, vcc ------------------------------------------------------------------------------------------------------- ? 0.3v to 6v ? boot to phase ------------------------------------------------------------------------------------------------------------ ? 0.3v to 6v ? phase to gnd dc -------------------------------------------------------------------------------------------------------------------------- ----- ? 0.3v to 32v < 20ns ---------------------------------------------------------------------------------------------------------------------- --- ? 8v to 38v ? ugate to phase dc -------------------------------------------------------------------------------------------------------------------------- ----- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- --- ? 5v to 7.5v ? lgate to gnd dc -------------------------------------------------------------------------------------------------------------------------- ----- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- --- ? 2.5v to 7.5v ? pwm, en to gnd ---------------------------------------------------------------------------------------------------------- ? 0.3v to 6v ? power dissipation, p d @ t a = 25 c wdfn-8l 2x2 ---------------------------------------------------------------------------------------------------------------- 2.19 w ? package thermal resista nce (note 2) wdfn-8l 2x2, ja ----------------------------------------------------------------------------------------------------------- 45.5 c/w wdfn-8l 2x2, jc ---------------------------------------------------------------------------------------------------------- 11.5 c/w ? junction temperature ------------------------------------------------------------------------------------------------------- 150 c ? lead temperature (soldering, 10 sec.) --------------------------------------------------------------------------------- 260 c ? storage temperature range ---------------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) ------------------------------------------------------------------------------------------------ 2kv
RT9610C 5 ds9610c-01 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit pwm input input current i pw m v pw m = 5v -- 174 -- ? a v pw m = 0v -- ? 174 -- pwm tri-state rising threshold v pw mh v cc = 5v 3.5 3.8 4.1 v pwm tri-state falling threshold v pw ml v cc = 5v 0.7 1 1.3 v en input en input voltage logic-high v enh v cc = 5v 1.4 -- -- v logic-low v enl v cc = 5v -- -- 0.48 switching time ugate rise time t ugater v cc = 5v, 3nf load -- 8 -- ns ugate fall time t ugatef v cc = 5v, 3nf load -- 8 -- ns lgate rise time t lgater v cc = 5v, 3nf load -- 8 -- ns lgate fall time t lgatef v cc = 5v, 3nf load -- 4 -- ns ugate turn-off propagation delay t pdlu v cc = 5v, outputs unloaded -- 35 -- ns lgate turn-off propagation delay t pdll v cc = 5v, outputs unloaded -- 35 -- ns ugate turn-on propagation delay t pdhu v cc = 5v, outputs unloaded -- 20 -- ns lgate turn-on propagation delay t pdhl v cc = 5v, outputs unloaded -- 20 -- ns ugate/lgate tri-state propagation delay t pts v cc = 5v, outputs unloaded -- 35 -- ns output ugate driver source resistance r ugatesr 100ma source current -- 1 -- ? ugate driver source current i ugatesr v ugate ?? v phase = 2.5v -- 2 -- a ugate driver sink resistance r ugatesk 100ma sink current -- 1 -- ? ugate driver sink current i ugatesk v ugate ?? v phase = 2.5v -- 2 -- a lgate driver source resistance r lgatesr 100ma source current -- 1 -- ? lgate driver source current i lgatesr v lgate = 2.5v -- 2 -- a lgate driver sink resistance r lgatesk 100ma sink current -- 0.5 -- ? lgate driver sink current i lgatesk v lgate = 2.5v -- 4 -- a note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution recommended. the human body mode is a 100pf capacitor is charged through a 1.5k resistor into each pin. note 4. the device is not guaranteed to function outside its operating conditions.
RT9610C 6 ds9610c-01 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit timing diagram pwm lgate ugate t pdll 90% 1.5v 1.5v t pdhu t pdlu t pdhl 90% 1.5v 1.5v vcc pwm gnd boot ugate phase lgate RT9610C 1f q1 v cc 1f pwm 1h 2.2h v core q2 en c1 c2 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 r1 r2 r3 r4 l1 l2 v in v bat 3.3nf c3 2.2 r5 enable
RT9610C ? ds9610c-01 april 2016 www.richtek.com 7 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics dead time ugate phase lgate ugate - phase (5v/div) time (20ns/div) v in = 19v, pwm falling, no load dead time ugate phase (5v/div) lgate ugate - phase time (20ns/div) v in = 19v, pwm rising, no load pwm rising edge ugate (20v/div) phase (20v/div) pwm (5v/div) lgate (5v/div) time (20ns/div) v in = 19v, no load pwm falling edge ugate (20v/div) phase (20v/div) pwm (5v/div) lgate (5v/div) time (20ns/div) v in = 19v, no load driver disable ugate (20v/div) phase (20v/div) en (5v/div) lgate (5v/div) time (1 s/div) v in = 19v, no load driver enable ugate (20v/div) phase (20v/div) en (5v/div) lgate (5v/div) time (1 s/div) v in = 19v, no load
RT9610C 8 ds9610c-01 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. short pulse ugate phase lgate ugate - phase (5v/div) time (20ns/div) v in = 19v, start up dead time ugate phase lgate ugate - phase (5v/div) time (20ns/div) v in = 19v, pwm falling, full load dead time ugate phase lgate ugate - phase (5v/div) time (20ns/div) v in = 19v, pwm rising, full load
RT9610C 9 ds9610c-01 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information supply voltage and power on reset the RT9610C is designed to drive both high side and low side n-mosfets through an externally input pwm control signal. connect 5v to vcc to power on the RT9610C. a minimum 1 f ceramic capacitor is recommended to bypass the supply voltage. place the bypassing capacitor physically near the ic. the power on reset (por) circuit monitors the supply voltage at the vcc pin. if vcc exceeds the por rising threshold voltage, the controller resets and prepares for operation. ugate and lgate are held low before vcc is above the por rising threshold. enable and disable the RT9610C includes an en pin for sequence control. when the en pin rises above the v enh trip point, the RT9610C begins a new initialization and follows the pwm command to control the ugate and lgate. when the en pin falls below the v enl trip point, the RT9610C shuts down and keeps ugate and lgate low. three state pwm input after initialization, the pwm signal takes over the control. the rising pwm signal first forces the lgate signal low and then allows the ugate signal to go high right after a non-overlapping time to avoid shoot through current. in contrast, the falling pwm signal first forces ugate to go low. when the ugate or phase signal reach a predetermined low level, lgate signal is then allowed to go high. non-overlap control to prevent the overlap of the gate drives during the ugate pull low and the lgate pull high, the non-overlap circuit monitors the voltages at the phase node and high side gate drive (ugate-phase). when the pwm input signal goes low, ugate begins to pull low (after propagation delay). before lgate can pull high, the non-overlap protection circuit ensures that the monitored (ugate- phase) voltages have gone below 1.1v or phase voltage is below 2v. once the monitored voltages fall below the threshold, lgate begins to turn high. by waiting for the voltages of the phase pin and high side gate drive to fall below their threshold, the non-overlap protection circuit ensures that ugate is low before lgate pulls high. also to prevent the overlap of the gate drives during lgate pull low and ugate pull high, the non-overlap circuit monitors the lgate voltage. when lgate go below 1.1v, ugate is allowed to go high. driving power mosfets the dc input impedance of the power mosfet is extremely high. the gate draws the current only for few nano-amperes. thus once the gate has been driven up to ? on ? level, the current could be negligible. however, the capacitance at the gate to source terminal should be considered. it requires relatively large currents to drive the gate up and down rapidly. it is also required to switch drain current on and off with the required speed. the required gate drive currents are calculated as follows. l s 2 c gs1 c gd1 i gd1 i gs1 i g1 v out s 1 v in d 1 d 1 gnd g 1 d 2 c gs2 g 2 i g2 i gd2 i gs2 c gd2 d 2 figure1. equivalent circuit and associated waveforms 5v t t v g2 v g1 v phase +5v
RT9610C 10 ds9610c-01 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. in figure 1, the current i g1 and i g2 are required to move the gate up to 5v. the operation consists of charging c gd1 , c gd2 , c gs1 and c gs2 . c gs1 and c gs2 are the capacitors from gate to source of the high side and the low side power mosfets, respectively. in general data sheets, the c gs1 and c gs2 are referred as ? c iss ? which are the input capacitors. c gd1 and c gd2 are the capacitors from gate to drain of the high side and the low side power mosfets, respectively and referred to the data sheets as ? c rss ? the reverse transfer capacitance. for example, t r1 and t r2 are the rising time of the high side and the low side power mosfets respectively, the required current i gs1 and i gs2 , are shown as below : ?? ?? g1 gs1 gs1 gs1 r1 g2 gs1 gs2 gs1 r2 dv c x 5 ic dt t dv c x 5 ic dt t before driving the gate of the high side mosfet up to 5v, the low side mosfet has to be off; and the high side mosfet is turned off before the low side is turned on. from figure 1, the body diode ? d 2 ? had been turned on before high side mosfets turned on. (1) (2) ?? gd1 gd1 gd1 r1 dv 5 ic c dt t (3) before the low side mosfet is turned on, the c gd2 have been charged to v in . thus, as c gd2 reverses its polarity and g 2 is charged up to 5v, the required current is : ? ?? gd2 gd2 gd2 r2 dv vi 5 ic c dt t (4) it is helpful to calculate these currents in a typical case. assume a synchronous rectified buck converter, input voltage v in = 12v, v g1 = v g2 = 5v. the high side mosfet is phb83n03lt whose c iss = 1660pf, c rss = 380pf, and t r = 14ns. the low side mosfet is phb95n03lt whose c iss = 2200pf, c rss = 500pf and t r = 30ns, from the equation (1) and (2) we can obtain : ?? ?? -12 gs1 -9 -12 gs2 -9 1660 x 10 x 5 i 0.593 (a) 14 x 10 2200 x 10 x 5 i 0.367 (a) 30 x 10 (5) (6) from equation. (3) and (4) ?? ?? ?? -12 gd1 -9 -12 gd2 -9 380 x 10 x 5 i 0.136 (a) 14 x 10 500 x 10 x 12+5 i 0.283 (a) 30 x 10 (7) (8) the total current required from the gate driving source can be calculated as following equations : by a similar calculation, we can also get the sink current required from the turned off mosfet. select the bootstrap capacitor figure 2 shows part of the bootstrap circuit of the RT9610C. the v cb (the voltage difference between boot and phase on RT9610C) provides a voltage to the gate of the high side power mosfet. this supply needs to be ensured that the mosfet can be driven. for this, the capacitance c b has to be selected properly. it is determined by following constraints. ?? ?? ??? ? ? ??? ? ? g1 gs1 gd1 g2 gs2 gd2 i i i 0.593 0.136 0.729 (a) i i i 0.367 0.283 0.65 (a) (9) (10) v in c b v cb + - boot v cc ugate phase lgate gnd figure 2. part of bootstrap circuit of RT9610C in practice, a low value capacitor c b will lead to the over charging that could damage the ic. therefore, to minimize the risk of overcharging and to reduce the ripple on v cb , the bootstrap capacitor should not be smaller than 0.1 f, and the larger the better. in general design, using 1 f can provide better performance. at least one low esr capacitor should be used to provide good local de-coupling. it is recommended to adopt a ceramic or tantalum capacitor.
RT9610C 11 ds9610c-01 april 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn-8l 2x2 packages, the thermal resistance, ja , is 45.5 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (45.5 c/w) = 2.19w for wdfn-8l 2x2 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curves in figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 3. derating curve of maximum power dissipation figure 4. synchronous buck converter circuit when layout the pcb, it should be very careful. the power circuit section is the most critical one. if not configured properly, it will generate a large amount of emi. the junction of q1, q2, l2 should be very close. next, the trace from ugate, and lgate should also be short to decrease the noise of the driver output signals. phase signals from the junction of the power mosfet, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. the bypass capacitor c4 should be connected to gnd directly. furthermore, the bootstrap capacitors (c b ) should always be placed as close to the pins of the ic as possible. layout considerations figure 4 shows the schematic circuit of a synchronous buck converter to implement the RT9610C. boot ugate phase lgate vcc RT9610C 1 5 4 7 8 gnd 3 cb 12v l1 c3 v in v core c2 phb83n03lt phb95n03lt l2 q2 q1 c1 + + 5v pwm 2 pwm 6 5v c4 r1 en 0.0 0.5 1.0 1.5 2.0 2.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT9610C 12 ds9610c-01 april 2016 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. w-type 8l dfn 2x2 package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 1.950 2.050 0.077 0.081 d2 1.000 1.250 0.039 0.049 e 1.950 2.050 0.077 0.081 e2 0.400 0.650 0.016 0.026 e 0.500 0.020 l 0.300 0.400 0.012 0.016 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a outline dimension

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